The present invention relates to a semiconductor integrated circuit device, and more particularly to a technology which can be effectively utilized in a semiconductor integrated circuit device containing, for instance, a dynamic random access memory (RAM) with a built-in intermediate voltage generating circuit formed by dividing the source voltage.
A dynamic RAM (DRAM) requires a circuit for generating a voltage HVDL, which is half the bit line voltage VDL for precharging bit lines or biasing memory cell plates. Capacities of DRAMs have been increased progressively in recent years, resulting in designs on a gigabit scale. Such a large-capacity DRAM requires a circuit system capable of supplying a large current because the capacities of bit lines and memory cell plates therein reach hundreds of nF.
FIG. 6 illustrates a bit line precharging voltage generating circuit according to the prior art. This circuit is described in The Institute of Electronics, Information and Communication Engineers, Prepared Papers for the 1990 Autumn Convention (in Japanese), Vol. 5, p. 252. It basically consists of a push-pull load driving circuit comprising a P-channel type MOSFET and an N-channel type MOSFET, and two error amplifiers A1 and A2 for individually driving them. The operating currents of these amplifiers A1 and A2 are controlled by the outputs of smaller amplifiers A3 and A4, respectively.
Into this circuit are entered two different voltages, resulting from the division of a source voltage VCC by a resistor, as reference voltages for determining its output voltage Vout. Of the two reference voltages, the lower one V1 is entered into the amplifier A1 for driving the P-channel type MOSFET, while the higher voltage V2 is entered into the amplifier A2 for driving the N-channel type MOSFET. This results in the formation of an insensitive region in the relationship between the output voltage and the output amperage of this circuit as shown in FIG. 2. This insensitive region is intended to prevent a constant penetrate penetrating current from passing the P-channel type MOSFET and the N-channel type MOSFET.
This circuit is further provided with the amplifiers A3 and A4 smaller than the amplifiers A1 and A2 both in device size and in amperage. One (+) of the input terminals of each of these smaller amplifiers A3 and A4 is supplied with the output voltage Vout of this circuit. The other input (xe2x88x92) of the smaller amplifier A3 is supplied, if it matches the P-channel type MOSFET, with a voltage lower than the voltage V1, and that matching the N-channel type MOSFET, with a voltage V4 higher than the voltage V4.
When a load current flows with the result of a drop in the output voltage Vout beyond the input voltage V3 of the smaller amplifier A3, its output signal takes on a low level and the output of a NAND gate circuit, a high level. This increases the operating current of the amplifier forming the gate voltage of the P-channel type MOSFET to quickly reduce the gate voltage of the P-channel type MOSFET toward the low level. As a result, the output voltage Vout rises to return to its original level. Conversely, the inflow of a load current results in a rise in the output voltage Vout beyond the input voltage V4 of the smaller amplifier A3, its output signal takes on a high level and the output of the NOR gate circuit, a low level. This increases the operating current of the amplifier A2 forming the gate voltage of the N-channel type MOSFET to quickly raise the gate voltage of the N-channel type MOSFET toward the high level. As a result, the output voltage Vout drops and returns to its original level.
However, this circuit indispensably requires resistors because as many as four different accurate reference voltages V1 through V4 are needed to generate the insensitive region and to detect the level of current switching. There is involved another problem that resistance elements of high resistances are required to reduce the currents flowing to the resistors, and they occupy a relatively large space. Furthermore, a current should be flowed all the time to detect the level of current switching, inviting a correspondingly greater consumption of power.
An object of the present invention is to provide a semiconductor integrated circuit device equipped with an intermediate voltage generating circuit which can achieve circuitry simplification and a saving in power consumption. Another object of the invention is to provide a semiconductor integrated circuit device equipped with an intermediate voltage generating circuit which consumes less power and excels in responsiveness. These and other objects and novel characteristics of the invention will become apparent from the description in this specification when taken in conjunction with the accompanying drawings.
To briefly describe some typical aspects of the invention disclosed in this patent application, a semiconductor integrated circuit containing within its chip a voltage generating circuit for generating an external source voltage VDD or a voltage which is half a voltage internally generated on the basis of that external voltage, the voltage generating circuit consisting of two sets of differential circuits for comparing a reference voltage and the output voltage of a push-pull output circuit and driving the output transistor of the push-pull output circuit, and the differential circuits being provided with offsets to prevent a penetrating current from flowing to the push-pull output circuit. The offsets are formed by differentiating the channel width/channel length ratios or the threshold voltages of differential pairs of MOSFETs. The bias currents of the differential circuits are made proportional to the respective load currents.